Performance Study of Energy Recovery Logic and Conventional CMOS Full Adder

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Single Phase Energy Recovery Logic and Conventional CMOS Logic: A Comparative Analysis

Extensive research is carried-out worldwide to design energy-efficient adiabatic circuits for such biomedical and space applications where conventional energy is limited and speed is not critical. In this paper a new single phase adiabatic or energy recovery logic is proposed and extensively analyzed the energy performance with technology scaling. We present a comparative study among proposed l...

متن کامل

Relative Performance Analysis of Different CMOS Full Adder Circuits

Different adder circuits are elementary blocks in many contemporary integrated circuits, which are not only employed to perform addition operations, but also other arithmetic operations such as subtraction, multiplication and division. Full adder is the basic building block of any adder circuit. Area, speed and power are the three main design metrics for any VLSI circuit. In this work, eight di...

متن کامل

A Novel High-Performance CMOS 1-Bit Full-Adder Cell

In this paper we introduced low leakage 10T one-bit full adders cells are proposed for mobile applications. The analysis has been performed on various process and circuits techniques, the analysis with leakage power. We introduced a new transistor resizing approach for 1bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power and area to minimize leakag...

متن کامل

A Novel Low Power Energy Recovery Full Adder Cell

A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low power full adders; the transmission function adder (TFA), the dual value logic (DVL) adder and the fourteen transistor (14T) full adder. The proposed SERF adder design was proven to...

متن کامل

Complementary Energy Path Adiabatic Logic based Full Adder Circuit

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adde...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: International Journal of Computer Applications

سال: 2016

ISSN: 0975-8887

DOI: 10.5120/ijca2016909887